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Formal Verification Engineer

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  • Knowledge of Formal verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc
  • 5+ years of experience in Formal Verification
  • Proven understanding of formal verification methodologies, complexity reduction techniques and abstraction techniques
  • Proven analytical skills to craft novel and creative solutions to tackle industry-level complex designs •Proven communication skills to ensure effective collaboration with cross functional teams
  • Fluency in hardware description languages, such as SystemVerilog and SVA
  • Proficiency in scripting languages such as Python, Perl, or Tcl
  • Experience with JasperGold or VC-Formal

Education: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience

Experience level: 8+ Years